All-digital clock deskew buffer with variable duty cycles
Journal
IEICE Transactions on Electronics
Journal Volume
E89-C
Journal Issue
6
Pages
753-759
Date Issued
2006
Author(s)
Kao, S.-K.
Abstract
An all-digital clock deskew buffer with variable duty cycles is presented. The proposed circuit aligns the input and output clocks with two cycles. A pulsewidth detector using the sequential time-to-digital conversion is employed to detect the duty cycle. The output clock with adjustable duty cycles can be generated. The proposed circuit has been fabricated in a 0.35 �gm CMOS technology. The measured duty cycle of the output clock can be adjusted from 30% to 70% in steps of 10%. The operation frequency ranee is from 400MHz to 600MHz.
SDGs
Type
journal article