Clock-deskew buffer using a SAR-controlled delay-locked loop
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
35
Journal Issue
8
Pages
1128-1136
Date Issued
2000
Author(s)
Abstract
A successive approximation register-controlled delay-locked loop (SARDLL) has been fabricated in a 0.25-/spl mu/m standard n-well DPTM CMOS process to realize a fast-lock clock-deskew buffer for long distance clock distribution. This DLL adopts a binary search method to shorten lock time while maintaining tight synchronization between input and output clocks. The measured lock time of the proposed SARDLL is within 30 clock cycles at 100-MWz clock input. The power dissipation is 3.3 mW (not including off-chip driver's) at a 1.1-V supply voltage while the measured rms and peak-to-peak jitter are 11.3 ps and 95 /spl mu/s, respectively.
SDGs
Type
journal article