A digital MDLL using switched biasing technique to reduce low-frequency phase noise
Journal
2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings
Pages
101-104
Date Issued
2017
Author(s)
Abstract
A digital multiplying delay-locked loop (DMDLL) is presented to reduce the low-frequency phase noise and lower the power. The main divider is also turned off to reduce the power. The digitally-controlled oscillator uses the switched biasing technique to reduce the low-frequency phase noise. This DMDLL is fabricated in 40-nm CMOS technology and its active area is 0.0088 mm 2 . The output frequency of the DMDLL ranges from 100 to 1050MHz for a supply voltage of 1.1V. The integrated RMS jitter is 2.68ps and the power consumption is 1.51mW at the output frequency of 1050MHz.
SDGs
Type
conference paper