A digital phase-locked loop with background supply voltage sensitivity minimization
Journal
IEEE Transactions on Circuits and Systems I: Regular Papers
Journal Volume
65
Journal Issue
6
Pages
1830-1839
Date Issued
2018
Author(s)
Tien, C.-W.
Abstract
A digital phase-locked loop (DPLL) with the background supply voltage sensitivity minimization is presented. By using a frequency subtractor, a digital supply voltage sensitivity controller can suppress the supply voltage sensitivity of a DPLL. This DPLL is fabricated in 40-nm CMOS technology. Its active area is 0.006 mm2 where the supply voltage sensitivity controller occupies about 20%. The power consumption is 9.34 mW from a supply of 1.1 V wherein the supply voltage sensitivity controller consumes μW. The output frequency of the DPLL is 5 GHz with a divider ratio of 64. The minimum measured supply voltage sensitivity is -0.0044]. With a 50-mVPP, 100-kHz sinusoidal supply noise, the peak-to-peak jitter is reduced from 41.48 to 23.15 ps, and the rms jitter is reduced from 7.26 to 3.47 ps. © 2004-2012 IEEE.
Subjects
Background; Frequency subtractor; Minimization; Phase-locked loop; Supply noise; Supply voltage sensitivity
SDGs
Other Subjects
Controllers; Jitter; Optimization; Background; Digital phase locked loops; Digital supply voltage; Peak-to-peak jitter; Sinusoidal supply; Subtractor; Supply noise; Supply voltages; Phase locked loops
Type
journal article