A 20-MHz to 3-GHz wide-range multiphase delay-locked loop
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
56
Journal Issue
11
Pages
850-854
Date Issued
2009
Author(s)
Chuang, C.-N.
Abstract
A 20-MHz to 3-GHz wide-range multiphase delay-locked loop (DLL) has been realized in 90-nm CMOS technology. The proposed delay cell extends the operation frequency range. A scaling circuit is adopted to lower the large delay gain when the frequency of the input clock is low. The core area of this DLL is 0.005 mm2. The measured power consumption values are 0.4 and 3.6 mW for input clocks of 20 MHz and 3 GHz, respectively. The measured peak-to-peak and root-mean-square jitters are 2.3 and 16 ps at 3 GHz, respectively. © 2009 IEEE.
Subjects
Delay cell; Delay-locked loop (DLL); Multiphase; Wide range
SDGs
Other Subjects
Clocks; Consumption values; Delay cell; Delay-locked loops; Large delays; Multiphase; Operation frequency ranges; Root Mean Square; Wide range; Delay lock loops
Type
journal article