https://scholars.lib.ntu.edu.tw/handle/123456789/499887
標題: | A 10-bit 40-MS/s Time-Domain Two-Step ADC with Short Calibration Time | 作者: | Chen, L.-J. SHEN-IUAN LIU |
關鍵字: | calibration time; digital calibration; Time-domain; two-step ADC; voltage-To-Time converter | 公開日期: | 2016 | 卷: | 63 | 期: | 2 | 起(迄)頁: | 126-130 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A 10-bit 40-MS/s time-domain two-step analog-To-digital converter (ADC) in a 0.18-μm CMOS process is presented. The proposed ADC is realized without any high-gain amplifiers and its calibration time requires only 622 clock cycles, which is over 10 times less than prior digitally calibrated ADCs. The measured spurious-free dynamic range (SFDR) and signal-To-noise-plus distortion ratio (SNDR) are 61.3 dB and 53.8 dB at 40 MS/s, respectively. The power and area are 6.1 mW and 0.75 mm2, respectively. © 2004-2012 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/499887 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84962262987&doi=10.1109%2fTCSII.2015.2483360&partnerID=40&md5=3b3ec88d6461634d41356659e3e4e5a3 |
ISSN: | 15497747 | DOI: | 10.1109/TCSII.2015.2483360 | SDG/關鍵字: | Calibration; Signal to noise ratio; Calibration time; Digital calibrations; Time domain; two-step ADC; Voltage-to-time converter; Analog to digital conversion |
顯示於: | 電機工程學系 |
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