A 12-bit 3.4 MS/s two-step cyclic time-domain ADC in 0.18-μm CMOS
Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal Volume
24
Journal Issue
4
Pages
1470-1483
Date Issued
2016
Author(s)
Chen, L.-J.
Abstract
Two two-step cyclic time-domain analog-to-digital converters (TADCs) in a 0.18-μm CMOS process are presented. The proposed TADC uses a voltage-to-time converter (VTC) with a 12-dB gain amplifier, and a time amplifier to achieve a 12-bit resolution. Only linear gain calibration is needed for the TADC. The first TADC achieves a spurious-free dynamic range (SFDR) of 70.5-dB and a signal-to-noise-plus distortion ratio (SNDR) of 64.3 dB. Its power consumption and area are 3 mW and 0.61 mm 2 , respectively. The noise analysis for each TADC building block is presented. The calculated results are verified by the transient noise analysis tool in HSPICE. To verify the noise analysis further, a second TADC is fabricated using the VTC with the device size scaled down by a factor of 4 based on the noise analysis. The second TADC achieves an SFDR of 66.8 dB and an SNDR of 59.1 dB. Its power consumption and area are 2.9 mW and 0.61 mm 2 , respectively.
SDGs
Type
journal article