A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction
Journal
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Journal Volume
2015-August
Pages
C138-C139
Date Issued
2015
Author(s)
Kuan, T.-K.
Abstract
This paper presents a digital bang-bang phase-locked loop that employs automatic loop gain control and loop latency reduction techniques to enhance the jitter performance. The chip is fabricated in a 40nm CMOS process. This bang-bang phase-locked loop achieves 290fs rms integrated jitter and reference spurs <-72.89dBc. It consumes 3.8mW from a 1.1V supply while operating at 3.96GHz. This translates to an FOM of −245dB.
SDGs
Type
conference paper