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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Design and Analysis of Defect Tolerant Hierarchical Sorting Networks
Details
Design and Analysis of Defect Tolerant Hierarchical Sorting Networks
Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal Volume
1
Journal Issue
2
Pages
219-223
Date Issued
1993
Author(s)
Kuo, S.-Y.
Liang, S.-C.
SY-YEN KUO
DOI
10.1109/92.238413
URI
https://scholars.lib.ntu.edu.tw/handle/123456789/500887
URL
https://www.scopus.com/inward/record.uri?eid=2-s2.0-0027614654&doi=10.1109%2f92.238413&partnerID=40&md5=d2938b43b55f636ec1e6710518aada22
Type
journal article