Scalable arithmetic cells for iterative logic array
Journal
Proceedings of ICECE 2008 - 5th International Conference on Electrical and Computer Engineering
Pages
325-330
Date Issued
2008
Author(s)
Abstract
In this paper, we propose a novel test technique to achieve both acceptable number of test patterns (NTP) and hardware overhead (HO) by finding a balance between them. Novel bijective and scalable cells are proposed to apply the technique on ILA-based (Iterative-Logic-Array) architectures. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable cells establish the relationship between HO and NTP. Both HO and NTP change as n varies. By adjusting the value of n, we can obtain an optimal balance between HO and NTP. The ILA based on these scalable cells will be still C-testable. We have C-testable design for MAC (Multiplier-Accumulator) and the (HO, NTP) for n = 2 are only (4.43%, 74). With bijective cells, all different ILA meshes can be connected into a bigger hybrid mesh for saving lots of test pins and BIST (Build-In Self Test) area. In addition, the proposed scalable cells induce a simple and systematic way to have balanced results. The proposed technique makes ILA-based DFT schemes more practical, systematic and useful for real complicated applications.
Type
conference paper