Error Recovery in Parallel Systems of Pipelined Processors with Caches.
Journal
Proceedings of the 1994 International Conference on Parallel Processing, North Carolina State University, NC, USA, August 15-19, 1994. Volume I: Architecture.
Pages
271-274
Date Issued
1994
Author(s)
Abstract
This paper examines the problem of recovering from processor transient faults in pipelined multiprocessor systems. A pipelined machine allows out of order instruction execution and branch prediction to increase performance, thus a precise computation state may not be available. We propose a modified scheme to implement the precise computation state in a pipelined machine. The goal of this research is to implement checkpointing and rollback for error recovery in a pipelined system based on the technique to achieving precise computation state. Detailed analysis has been performed to demonstrate the effectiveness of this method.
Type
conference paper