A 2 -8 GHz multi-phase distributed DLL using phase insertion in 90 nm
Journal
ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems
Pages
2015-2018
Date Issued
2012
Author(s)
Abstract
A 2 GHz to 8 GHz wide-range multi-phase distributed delay-locked loop (DDLL) has been proposed. The architecture achieves wide operating frequency range by adding a digital phase selector into the DDLL [1]. The insertion phases which are generated from digital phase selector with minor phase error could be fine-tuned by the voltage-controlled delay cells in the DDLL independently. The test chip was fabricated in TSMC 90 nm technology and occupies 0.0644 mm 2 active areas. The maximum phase error is 1.53 ps at 8 GHz, and 1.93 ps at 2 GHz respectively.
SDGs
Type
conference paper