An at-speed test technique for high-speed high-order adder by a 6.4-GHz 64-bit domino adder example

Journal

IEEE Transactions on Circuits and Systems I: Regular Papers

Journal Volume

59

Journal Issue

8

Pages

1644-1655

Date Issued

2012

Author(s)

Wang, Y.-S.

Hsieh, M.-H.

Li, J.C.-M.

CHUNG-PING CHEN

DOI

10.1109/TCSI.2012.2206503

URI

https://scholars.lib.ntu.edu.tw/handle/123456789/501065

URL

https://www.scopus.com/inward/record.uri?eid=2-s2.0-84864569486&doi=10.1109%2fTCSI.2012.2206503&partnerID=40&md5=69fb56addc6d44e1ab895f9b8bb242bf

SDGs

[SDGs]SDG7

Type

journal article