A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC

An 8-bit 1.5GS/s 2-way two-step SAR ADC operating at 0.9V is presented in this paper. A low-skew demultiplexer circuit is proposed to synchronize the sampled signals of the two sub-ADCs with the edge of global clock. The sharing of the quarter clock phase generator leads to lower power consumption. A charge-sharing technique without any interstage residue amplifier not only makes the two-step SAR sub-ADC low-power, but also accelerates its conversion rate. A self-trigger latch (STL) technique is also used to reduce digital power consumption. The prototype ADC in 40nm CMOS consumes 3.1mW at 1.5GS/s with a 0.9V supply. It achieves a Nyquist SNDR of 44.5dB and results in an FoM of 15fJ/c.-s. © 2016 IEEE.