https://scholars.lib.ntu.edu.tw/handle/123456789/501233| Title: | A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC | Authors: | Hu, Y.-S. Huang, P.-C. Yang, M.-T. Wu, S.-W. Chen, H.-S. HSIN-SHU CHEN |
Keywords: | Analog-to-digital converter (ADC); charge sharing; energy-efficient; low-skew demultiplexer; self-triggered latch; successive-approximation register (SAR); two-step | Issue Date: | 2017 | Start page/Pages: | 81-84 | Source: | 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings | Abstract: | An 8-bit 1.5GS/s 2-way two-step SAR ADC operating at 0.9V is presented in this paper. A low-skew demultiplexer circuit is proposed to synchronize the sampled signals of the two sub-ADCs with the edge of global clock. The sharing of the quarter clock phase generator leads to lower power consumption. A charge-sharing technique without any interstage residue amplifier not only makes the two-step SAR sub-ADC low-power, but also accelerates its conversion rate. A self-trigger latch (STL) technique is also used to reduce digital power consumption. The prototype ADC in 40nm CMOS consumes 3.1mW at 1.5GS/s with a 0.9V supply. It achieves a Nyquist SNDR of 44.5dB and results in an FoM of 15fJ/c.-s. © 2016 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/501233 | DOI: | 10.1109/ASSCC.2016.7844140 | SDG/Keyword: | Clocks; Demultiplexing; Electric power utilization; Energy efficiency; Analog to digital converters; Charge sharing; Demultiplexers; Energy efficient; self-triggered latch; Successive approximation register; two-step; Analog to digital conversion [SDGs]SDG7 |
| Appears in Collections: | 電機工程學系 |
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