https://scholars.lib.ntu.edu.tw/handle/123456789/501236
標題: | An 8-bit 900MS/S two-step SAR ADC | 作者: | Huang, P.-C. Hu, Y.-S. Tai, H.-Y. HSIN-SHU CHEN |
公開日期: | 2016 | 卷: | 2016-July | 起(迄)頁: | 2898- | 來源出版物: | Proceedings - IEEE International Symposium on Circuits and Systems | 摘要: | Several hundreds of MS/s to 1GS/s 8-bit low-power ADCs are demanded in various portable applications. Conventional successive-approximation register (SAR) architecture has the benefits of energy efficiency and small area but it suffers from low conversion rate. Recently, multi-bit per cycle SAR [1], multi-comparator SAR [2], pipeline-SAR, and time-interleaved SAR architectures [3] are reported to improve the conversion rate. In this work, an asynchronous two-step single-channel SAR ADC using a charge sharing technique and a self-triggered-latch (STL) technique is proposed to accelerate the conversion rate and reduce the power consumption. This ADC achieves 44.3dB SNDR and 19.1 fJ/c.-s. at 900MS/s with an active core area of 0.0049 mm2 in 40nm CMOS process. © 2016 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/501236 | DOI: | 10.1109/ISCAS.2016.7539201 | SDG/關鍵字: | Reconfigurable hardware; Charge sharing; Conversion rates; Multi-bits; Portable applications; Single channels; Small area; Successive approximation register; Time-interleaved; Energy efficiency |
顯示於: | 電機工程學系 |
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