A 5.28-Gb/s LDPC Decoder With Time-Domain Signal Processing for IEEE 802.15.3c Applications
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
52
Journal Issue
2
Pages
592-604
Date Issued
2017
Author(s)
Abstract
This paper presents a high-throughput, energy-efficient, and scalable low-density parity-check (LDPC) decoder with time-domain (TD) signal processing. The proposed arbiter-based minimum value finder is able to support practical long codes. The latency for determining the first two minimum values required in the check node unit is significantly reduced through TD processing. A layered Q-based decoding architecture together with the associated scheduling is proposed in order to reduce the amount of memory used for check node storage. Multimode operations are supported by leveraging the structure of the base matrices and the proposed scalable minimum finder architecture. As a proof of concept, a TD-based multimode LDPC decoder for high-speed IEEE 802.15.3c is designed and fabricated in a 90-nm CMOS process. The LDPC decoder integrates 495k logic gates in 2.25 mm2 and achieves a throughput of 5.28 Gb/s at 157 MHz from a 1.05 V supply voltage. The power and normalized energy dissipation are 182 mW and 34.47 pJ/b, respectively. The proposed LDPC decoder is more hardware and energy efficient than previous digital counterparts and is able to support long codes for practical applications, which is still infeasible for the state-of-the-art TD-based LDPC decoders. © 2017 IEEE.
Subjects
CMOS integrated circuits; IEEE 802.15.3c; layered scheduling; low-density parity-check (LDPC) code; time-domain (TD) signal processing; wireless personal area network
SDGs
Other Subjects
Decoding; Energy dissipation; Energy efficiency; Satellite communication systems; Check node units; Digital counterparts; Energy efficient; Low density parity check decoders (LDPC); Multimode operations; Proof of concept; State of the art; Time-domain signal; Signal processing
Type
journal article