A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition
Journal
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Date Issued
2009
Author(s)
Abstract
A linear CDR circuit manifests itself in easy modeling and minimal activity on phase adjustment under locked condition. However, linear PDs face a speed limitation at around 10 Gb/s, primarily because of the required pulsewidth comparison and finite flip-flop CK-to-Q delay. Parallelism could relax the stringent speed requirement, but it also introduces other issues such as clock skews and jitters. Frequency acquisition without an external reference such as Pottbacker FD and other similar approaches require quadrature clocks, potentially leading to higher phase noise as well. This paper presents the design and analysis of a 20 Gb/s full-rate CDR circuit in 90 nm CMOS, which completely eliminates the conventional issues by using an alternative linear PD structure and a referenceless FD with automaticity.
SDGs
Type
conference paper