A 2x25Gb/s deserializer with 2:5 DMUX for 100Gb/s ethernet applications
Journal
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Journal Volume
53
Pages
374-375
Date Issued
2010
Author(s)
Wu, K.-C.
Abstract
A 2 × 25 Gb/s deserializer for 100 Gb/s Ethernet is implemented in 65 nm CMOS technology. Employing regulated limiting amplifiers, full-rate CDRs, a built-in clock generator, and a 2:5 DMUX, this two-channel prototype achieves BER -12 with 20 mV pp input sensitivity while consuming a total power of 510 mW.
Type
conference paper