Pipeline interleaving design for FIR, IIR, and FFT array processors
Journal
Journal of VLSI Signal Processing
Journal Volume
10
Journal Issue
3
Pages
275-293
Date Issued
1995
Author(s)
Abstract
In this paper, a floating point multiply- and-accumulate (FMAC) processor capable of running the FIR, IIR, and FFT algorithms is proposed. This processor executes many independent FMAC operations circularly without causing any hazard. The algorithmic processing is decomposed into independent subprocesses, each of which executes a FMAC group and all of the subprocesses are activated in turn. The projection method of VLSI array processors is used to map the data flow of FIR, IIR, and FFT into subprocesses so that the algorithms can be successfully executed by the processor in the way of pipeline interleaving. Because of the 100% utilization of pipeline, a very good performance is achieved. © 1995 Kluwer Academic Publishers.
SDGs
Type
journal article