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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Pipeline interleaving design for FIR, IIR, and FFT array processors
Details
Pipeline interleaving design for FIR, IIR, and FFT array processors
Journal
Journal of VLSI Signal Processing
Journal Volume
10
Journal Issue
3
Pages
275-293
Date Issued
1995
Author(s)
Chen, L.-G.
Jehng, Y.-S.
LIANG-GEE CHEN
TZI-DAR CHIUEH
DOI
10.1007/BF02120033
URI
https://scholars.lib.ntu.edu.tw/handle/123456789/502369
URL
https://www.scopus.com/inward/record.uri?eid=2-s2.0-0029349867&doi=10.1007%2fBF02120033&partnerID=40&md5=085387acfec71cee8e69e29e8ad81d49
SDGs
[SDGs]SDG7
Type
journal article