A Static RAM Chip with On-Chip Error Correction
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
25
Journal Issue
5
Pages
1290-1294
Date Issued
1990
Author(s)
Abstract
This paper describes a 2-kb CMOS static RAM with on-chip error-correction capability (ECCRAM chip). The chip employs the linear sum code (LSC) technique to perform error detection and correction. The ECCRAM chip has been fabricated in a double-metal scalable CMOS process with 3-μm feature size. Testing results of the actual chip shows a significant improvement in random error tolerance. © 1990 IEEE
Other Subjects
Codes, Symbolic - Error Correction; Data Storage, Digital - Random Access; Integrated Circuits, CMOS; Semiconductor Devices, MOS - Applications; CMOS Technology; Static Random-Access Memory (SRAM); Data Storage, Semiconductor
Type
journal article