Parallel Architectures for 3-Step Hierarchical Search Block-Matching Algorithm
Journal
IEEE Transactions on Circuits and Systems for Video Technology
Journal Volume
4
Journal Issue
4
Pages
407-416
Date Issued
1994
Author(s)
Abstract
The paper describes fully pipelined parallel architectures for the 3-step hierarchical search block-matching algorithm, a fast motion estimation algorithm for video coding. The advantage of this algorithm was completely utilized by use of intelligent data arrangement and memory configuration. Techniques for reducing interconnections and external memory accesses were also developed. Because of their low costs, high speeds, and low memory bandwidth requirements, the proposed 3-PE, 9-PE, and 27-PE architectures provide efficient solutions for real-time motion estimations required by video applications of various data rates, from low bit-rate video to HDTV systems.>
Type
journal article