Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits
Journal
Proceedings of the Asian Test Symposium
Journal Volume
2016-February
Pages
181-186
Date Issued
2015
Author(s)
Abstract
A FAST fault model is proposed for small delay faults induced by cross-gate defects in FinFET. FAST ATPG, fault simulation, and test selection are presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL respectively than those of commercial tool timing-unaware 1-detect pattern sets.
Type
conference paper