https://scholars.lib.ntu.edu.tw/handle/123456789/505966| Title: | Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits | Authors: | Chiang, K.-Y. Ho, Y.-H. Chen, Y.-W. Pan, C.-S. Li, J.C.-M. CHIEN-MO LI |
Issue Date: | 2015 | Journal Volume: | 2016-February | Start page/Pages: | 181-186 | Source: | Proceedings of the Asian Test Symposium | URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/505966 | DOI: | 10.1109/ATS.2015.38 |
| Appears in Collections: | 電機工程學系 |
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