Robust test pattern generation for hold-time faults in nanometer technologies

Journal

2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017

Date Issued

2017

Author(s)

Ho, Y.-H.

Chen, Y.-W.

Chang, C.-M.

Yang, K.-C.

DOI

10.1109/VLSI-DAT.2017.7939647

URI

https://scholars.lib.ntu.edu.tw/handle/123456789/505984

URL

https://www.scopus.com/inward/record.uri?eid=2-s2.0-85021456154&doi=10.1109%2fVLSI-DAT.2017.7939647&partnerID=40&md5=c19cc85f9bd6837e1c5de0e362f1f1a5

Type

conference paper