Robust test pattern generation for hold-time faults in nanometer technologies
Journal
2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
Date Issued
2017
Author(s)
Abstract
Hold-time faults are gaining attention in modern technologies because of process variation, power supply noise, and etc. A path-based hold-time fault model is proposed to cover short paths to and from every flip-flop. In addition, the number of faults is linear to the number of flip-flops in the circuit. Two-timeframe circuit models are proposed for ATPG and fault simulation. We show that traditional path delay fault ATPG is not sufficient for hold-time faults. A hold-time fault ATPG is presented to generate robust test patterns. Experiments on large benchmark show that our test patterns are 42% shorter while 38% better in robust fault coverage than 1-detect stuck-at fault test sets. The results justify the need for hold-time fault ATPG.
Type
conference paper