https://scholars.lib.ntu.edu.tw/handle/123456789/516591
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Y.-N. Chen | en_US |
dc.contributor.author | C.-J. Chen | en_US |
dc.contributor.author | M.-L. Fan | en_US |
dc.contributor.author | Pin Su | en_US |
dc.contributor.author | C.-T. Chuang | en_US |
dc.contributor.author | VITA PI-HO HU | en_US |
dc.creator | Y.-N. Chen;C.-J. Chen;M.-L. Fan;V. P.-H. Hu;Pin Su;C.-T. Chuang | - |
dc.date.accessioned | 2020-10-07T01:23:14Z | - |
dc.date.available | 2020-10-07T01:23:14Z | - |
dc.date.issued | 2015 | - |
dc.identifier.issn | 20799268 | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/516591 | - |
dc.description.abstract | In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better Ion and Cg,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices. © 2015 by the authors; licensee MDPI, Basel, Switzerland. | - |
dc.relation.ispartof | Journal of Low Power Electronics and Applications | - |
dc.subject | Carry-lookahead adder (CLA); FinFET; Line-edge-roughness (LER); Tunnel FET (TFET); Work function variation (WFV) | - |
dc.title | Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits | en_US |
dc.type | journal article | en |
dc.identifier.doi | 10.3390/jlpea5020101 | - |
dc.identifier.scopus | 2-s2.0-84930937802 | - |
dc.relation.pages | 101-115 | - |
dc.relation.journalvolume | 5 | - |
dc.relation.journalissue | 2 | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.openairetype | journal article | - |
item.grantfulltext | none | - |
item.cerifentitytype | Publications | - |
item.fulltext | no fulltext | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Program in Semiconductor Device, Material, and Hetero-integration | - |
crisitem.author.orcid | 0000-0002-6216-214X | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Graduate School of Advanced Technology | - |
Appears in Collections: | 電機工程學系 |
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