|Title:||FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics||Authors:||M.-L. Fan
VITA PI-HO HU
|Keywords:||FinFET; negative bias temperature instability (NBTI); positive bias temperature instability (PBTI); static random access memory (SRAM); surface orientation; variability||Issue Date:||2011||Journal Volume:||58||Journal Issue:||3||Start page/Pages:||805-811||Source:||IEEE Transactions on Electron Devices||Abstract:||
This paper analyzes the impacts of intrinsic process variations and negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations on the stability/variability of 6T FinFET static random access memory (SRAM) cells with various surface orientations and gate dielectrics. Due to quantum confinement, (110)-oriented pull-down n-channel FETs with fin line-edge roughness (LER) show larger Vread,0 and Vtrip variations, thus degrading read static noise margin (RSNM) and its variability. Pull-up p-channel FETs with fin LER that are (100)-oriented show larger Vwrite,0 and Vtrip variations, hence degrade the variability of write SNM. The combined effects of intrinsic process variations and NBTI/PBTI-induced statistical variations have been examined to optimize the FinFET SRAM cells. Worst-case stress scenario for SNM stability/variability is analyzed. With the presence of both NBTI and PBTI in high-κ metal-gate FinFET SRAM, the RSNM suffers significant degradation as Vread,0 increases, whereas Vtrip simultaneously decreases. Variability comparisons for FinFET SRAM cells with different gate stacks (SiO2 and SiO2/HfO2) are also examined. Our paper indicates that the consideration of NBTI/PBTI-induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in terms of the μ/σ ratio in RSNM. © 2011 IEEE.
|ISSN:||00189383||DOI:||10.1109/ted.2010.2099661||SDG/Keyword:||FinFET; Negative bias temperature instability; Positive bias temperature instabilities; static random access memory (SRAM); surface orientation; variability; Cell membranes; Degradation; Field effect transistors; Fins (heat exchange); Gate dielectrics; Gates (transistor); Hafnium compounds; Integrated circuits; MESFET devices; Negative temperature coefficient; Optimization; Silicon compounds; Thermodynamic stability; Static random access storage|
|Appears in Collections:||電機工程學系|
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