https://scholars.lib.ntu.edu.tw/handle/123456789/559058
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Yeh, K.-W. | en_US |
dc.contributor.author | JIUN-LANG HUANG | en_US |
dc.date.accessioned | 2021-05-05T02:56:15Z | - |
dc.date.available | 2021-05-05T02:56:15Z | - |
dc.date.issued | 2020 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.url?eid=2-s2.0-85096352769&partnerID=40&md5=0ccac0b234e1f3f331f230c912c1e54f | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/559058 | - |
dc.description.abstract | Many parallel test pattern generation techniques have been proposed to speed up the test pattern generation (TPG) process. Focusing on acceleration, most of these techniques sacrifice determinism and often incur test set inflation. In this paper, a parallel TPG that exploits search space parallelism to improve fault coverage, called deterministic search-space parallel ATPG (DSSP-ATPG), is proposed. Static search space partitioning and dynamic search space allocation techniques are developed to coordinate the cooperating threads so as to reduce the thread idle time and ensure determinism. Experimental results on larger benchmark circuits and an industry circuit show that DSSP-TPG improves fault coverage as the thread count is increased. Furthermore, to speed up the TPG process, a hybrid ATPG scheme that integrates the DSSP-ATPG with a deterministic fault-parallel ATPG is implemented. By adjusting the extent of fault and search-space parallelism, the user can tune the hybrid ATPG towards higher fault coverage or more CPU time reduction. © 2020 IEEE. | - |
dc.relation.ispartof | Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 | - |
dc.subject.other | Benchmark circuit; Dynamic search; Fault coverages; Idle time; Parallel test; Search space partitioning; Search spaces; Test pattern generations; Testing | - |
dc.title | DSSP-ATPG: A Deterministic Search-Space Parallel Test Pattern Generator | en_US |
dc.type | conference paper | en |
dc.relation.conference | 4th IEEE International Test Conference in Asia, ITC-Asia 2020 | - |
dc.identifier.doi | 10.1109/ITC-Asia51099.2020.00033 | - |
dc.identifier.scopus | 2-s2.0-85096352769 | - |
dc.relation.pages | 124 - 129 | - |
item.fulltext | no fulltext | - |
item.cerifentitytype | Publications | - |
item.openairetype | conference paper | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.grantfulltext | none | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Program in Integrated Circuit Design and Automation | - |
crisitem.author.orcid | 0000-0002-9425-3855 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Graduate School of Advanced Technology | - |
顯示於: | 電機工程學系 |
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