https://scholars.lib.ntu.edu.tw/handle/123456789/559262
標題: | A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique | 作者: | Lin, C.-Y. Wang, T.-J. Hung, Y.-T. TSUNG-HSIEN LIN |
關鍵字: | fractional output divider; phase rotating technique | 公開日期: | 2020 | 來源出版物: | 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 | 摘要: | An open-loop fractional output divider (FOD) using phase rotating technique is presented. A phase rotating technique is adopted to reduce the dynamic range of digitalto-Time converter (DTC) for output jitter improvement. This prototype is implemented in a 90-nm CMOS process. It can operate over a frequency range of 0.635 MHz to 162.5 MHz. At 160-MHz output frequency, it consumes 6.29 mW from 1-V supply. The measured phase noises at 1-MHz offset is 135.8 dBc/Hz and it achieves 1.19 psrms integrated jitter (10 kHz to 30 MHz). © 2020 IEEE. |
URI: | https://www.scopus.com/inward/record.url?eid=2-s2.0-85093694947&partnerID=40&md5=a07171ae858605ebfd5a05aed909570f https://scholars.lib.ntu.edu.tw/handle/123456789/559262 |
DOI: | 10.1109/VLSI-DAT49148.2020.9196213 | SDG/關鍵字: | Jitter; Phase noise; 90-nm cmos; Dynamic range; Fractional divider; Frequency ranges; Multiple outputs; Open-loop; Output frequency; Rotating technique; VLSI circuits |
顯示於: | 電機工程學系 |
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