|Title:||Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS<inf>2</inf>FETs for SoC Scaling||Authors:||Hu, V.P.-H.
VITA PI-HO HU
|Keywords:||2-D material; area efficiency; back-end-of-The-line (BEOL); energy efficiency; monolithic 3-D (M3D) integration; SRAM||Issue Date:||2020||Journal Volume:||67||Journal Issue:||10||Start page/Pages:||4216-4221||Source:||IEEE Transactions on Electron Devices||Abstract:||
In this article, we propose an energy-efficient monolithic 3-D (M3D) three-Tier SRAM cell with back-end-of-The-line (BEOL) back-gated (BG) MoS2 FETs. The impacts of wire routing resistance and capacitance, gate topology of MoS2 FETs, and the layout optimization of multitier 6T SRAM cells have been comprehensively analyzed for SoC scaling through system-Technology co-optimization. SRAM plays an integral role in the performance of SoCs, and the performance can be improved by SRAM on logic integration. Compared with one-Tier BG SRAM cell design, the proposed monolithic three-Tier BG SRAM cell releases the impact of metal line resistance and shows a 44.3% reduction in cell area, 28.4% improvement in read access time, 21.3% improvement in dynamic energy, and 43.6% improvement in energy-delay product. The energy-and area-efficient three-Tier BG SRAM cell enables intelligent functionalities for the area-and energy-constrained edge computing devices. © 1963-2012 IEEE.
|DOI:||10.1109/TED.2020.3018099||metadata.dc.subject.other:||Cells; Computation theory; Cytology; Energy efficiency; Layered semiconductors; Molybdenum compounds; Product design; System-on-chip; Back end of the lines; Computing devices; Energy delay product; Energy efficient; Energy-constrained; Layout optimization; Logic integration; Read access time; Static random access storage
|Appears in Collections:||電機工程學系|
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