Unified Redistribution Layer Routing for 2.5D IC Packages
Journal
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Journal Volume
2020-January
Pages
331-337
Date Issued
2020
Author(s)
Abstract
A 2.5-dimensional integrated circuit, which introduces an interposer as an interface between chips and a package, is one of the most popular integration technologies. Multiple chips can be mounted on an interposer, and inter-chip nets are routed on redistribution layers (RDLs). In traditional designs, the wire widths and spacings are uniform (i.e., grid-based). To improve circuit performance in modern designs, however, variable widths and spacings are also often adopted (i.e., gridless designs). In this paper, we propose the first unified routing framework that can handle both grid-based and gridless routing on RDLs based on the modulus-based matrix splitting iteration method (MMSIM) and bipartite matching. The MMSIM-based method assigns each wire a rough position while considering multiple design rules, and bipartite matching is applied to further refine those positions. We also prove the optimality of our RDL routing framework for grid-based designs and validate it empirically. Experimental results show that our framework can solve all the gridless and grid-based designs provided by industry effectively and efficiently. In particular, our framework is general and readily extends to other routing (and some quadratic optimization) problems. © 2020 IEEE.
SDGs
Other Subjects
Computer aided design; Iterative methods; Quadratic programming; Timing circuits; Bipartite matchings; Circuit performance; Integration technologies; Modulus-based matrix splitting iteration methods; Quadratic optimization; Redistribution layers; Routing frameworks; Variable width; Integrated circuits
Type
conference paper