https://scholars.lib.ntu.edu.tw/handle/123456789/559306
標題: | Unified Redistribution Layer Routing for 2.5D IC Packages | 作者: | Chiang, C.-H. Chuang, F.-Y. YAO-WEN CHANG |
公開日期: | 2020 | 卷: | 2020-January | 起(迄)頁: | 331-337 | 來源出版物: | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 摘要: | A 2.5-dimensional integrated circuit, which introduces an interposer as an interface between chips and a package, is one of the most popular integration technologies. Multiple chips can be mounted on an interposer, and inter-chip nets are routed on redistribution layers (RDLs). In traditional designs, the wire widths and spacings are uniform (i.e., grid-based). To improve circuit performance in modern designs, however, variable widths and spacings are also often adopted (i.e., gridless designs). In this paper, we propose the first unified routing framework that can handle both grid-based and gridless routing on RDLs based on the modulus-based matrix splitting iteration method (MMSIM) and bipartite matching. The MMSIM-based method assigns each wire a rough position while considering multiple design rules, and bipartite matching is applied to further refine those positions. We also prove the optimality of our RDL routing framework for grid-based designs and validate it empirically. Experimental results show that our framework can solve all the gridless and grid-based designs provided by industry effectively and efficiently. In particular, our framework is general and readily extends to other routing (and some quadratic optimization) problems. © 2020 IEEE. |
URI: | https://www.scopus.com/inward/record.url?eid=2-s2.0-85083037994&partnerID=40&md5=b97d4bc0bc25fdcc678f4d8370f45a89 https://scholars.lib.ntu.edu.tw/handle/123456789/559306 |
DOI: | 10.1109/ASP-DAC47756.2020.9045359 | SDG/關鍵字: | Computer aided design; Iterative methods; Quadratic programming; Timing circuits; Bipartite matchings; Circuit performance; Integration technologies; Modulus-based matrix splitting iteration methods; Quadratic optimization; Redistribution layers; Routing frameworks; Variable width; Integrated circuits |
顯示於: | 電信工程學研究所 |
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