Latch clustering for timing-power co-optimization
Journal
Proceedings - Design Automation Conference
Journal Volume
2020-July
Date Issued
2020
Author(s)
Abstract
Latch clustering is a critical stage to reduce power consumption at cost of timing disruption during a modern SoC design flow. However, most existing latch clustering researches mitigate timing disruptions by indirectly minimizing latch displacement during clustering, which is inaccurate and insufficient for timing closure in the design flow. Further, most researches do not control the amount of inserted clock buffers during clustering, which is the key factor to provide flexibility for timing and power trade-off. To address the two issues above, this paper presents a novel timing-power co-optimized latch clustering framework: we augment an integer linear programming (ILP) formulation of a facility-location allocation (FLA) problem to (1) directly optimize timing with a path-based timing model and (2) accurately control the number of inserted buffers by the FLA formulation for power optimization. We evaluate the framework with a displacement-optimized clustering approach and a state-of-the-art approach. Experimental results show 46% total negative slack timing overhead reduction, and 21% reduction for total power consumption. © 2020 IEEE.
Subjects
Latch Clustering; Legalization; Physical Design; Power; Timing
SDGs
Other Subjects
Computer aided design; Cost reduction; Economic and social effects; Electric power utilization; Integer programming; Integrated circuit design; System-on-chip; Timing circuits; Clustering approach; Facility location allocations; Integer Linear Programming; Overhead reductions; Path-based timings; Power Optimization; State-of-the-art approach; Total power consumption; Reduction
Type
conference paper