https://scholars.lib.ntu.edu.tw/handle/123456789/580879
標題: | A 38-GHz High Linearity and High Efficiency Power Amplifier for 5G Applications in 65-nm CMOS | 作者: | Li X.-Y Chen Y.-C Wang Y Huang T.-W HUEI WANG TIAN-WEI HUANG |
關鍵字: | CMOS integrated circuits; Efficiency; CMOS processs; Common source; Error vector magnitude; High efficiency power amplifiers; High linearity; High-efficiency; Output stages; Small signal gain; Power amplifiers | 公開日期: | 2021 | 起(迄)頁: | 178-181 | 來源出版物: | 2020 50th European Microwave Conference, EuMC 2020 | 摘要: | A 38-GHz high linearity and high efficiency power amplifier is implemented in 65-nm CMOS process. To improve the back-off efficiency, transistors of the driver stage are biased in deep class-AB. Insertion loss from output stage matching is only 1 dB, resulting in high efficiency. A two-stage common source PA is designed to provide enough gain. This PA achieves a 20.5-dB small-signal gain, 14.6-dBm PSAT, 35.8% peak power-added efficiency (PAE), 13.1-dBm P1dB, and 30.1% PAE1dB. The linearity, which is measured in error vector magnitude (EVM) of 64-QAM with 250 MHz bandwidth, is better than -25 dB, at the power level of 10.1-dBm output power with 17% PAE. The chip size including all pads is 0.2964 mm2. ? 2021 EuMA. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85100941140&doi=10.23919%2fEuMC48046.2021.9338136&partnerID=40&md5=0dacbc78bde98de4b4e72af5b3774b92 https://scholars.lib.ntu.edu.tw/handle/123456789/580879 |
DOI: | 10.23919/EuMC48046.2021.9338136 |
顯示於: | 電機工程學系 |
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