|Title:||First demonstration of heterogenous complementary FETs utilizing Low-Temperature (200 °c) Hetero-Layers Bonding Technique (LT-HBT)||Authors:||Hong T.-Z
JIUN-YUN LI et al.
|Keywords:||Chemical bonds; Electron devices; Silicon wafers; Surface treatment; Temperature; Bonding techniques; Chemical treatments; Heterogeneous integration; Layer transfer; Low temperatures; Multi-channel structure; Two channel; Wafer scale; Wafer bonding||Issue Date:||2020||Journal Volume:||2020-December||Source:||Technical Digest - International Electron Devices Meeting, IEDM||Abstract:||
For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration. ? 2020 IEEE.
|Appears in Collections:||電機工程學系|
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