https://scholars.lib.ntu.edu.tw/handle/123456789/581011
標題: | First demonstration of heterogenous complementary FETs utilizing Low-Temperature (200 °c) Hetero-Layers Bonding Technique (LT-HBT) | 作者: | Hong T.-Z. Chang W.-H. Agarwal A. Huang Y.-T. Yang C.-Y. Chu T.-Y. Chao H.-Y. Chuang Y. Chung S.-T. Lin J.-H. Luo S.-M. Tsai C.-J. Li M.-J. Yu X.-R. Lin N.-C. Cho T.-C. Sung P.-J. Su C.-J. Luo G.-L. Hsueh F.-K. Lin K.-L. Ishii H. Irisawa T. Maeda T. Wu C.-T. Ma W.C.-Y. Lu D.-D. Kao K.-H. Lee Y.-J. Chen H.J.-H. Lin C.-L. Chuang R.W. Huang K.-P. Samukawa S. Li Y.-M. Tarng J.-H. Chao T.-S. Miura M. Huang G.-W. Wu W.-F. JIUN-YUN LI Shieh J.-M. Wang Y.-H. Yeh W.-K. |
關鍵字: | Chemical bonds; Electron devices; Silicon wafers; Surface treatment; Temperature; Bonding techniques; Chemical treatments; Heterogeneous integration; Layer transfer; Low temperatures; Multi-channel structure; Two channel; Wafer scale; Wafer bonding | 公開日期: | 2020 | 卷: | 2020-December | 起(迄)頁: | 15.5.1 - 15.5.4 | 來源出版物: | Technical Digest - International Electron Devices Meeting, IEDM | 會議論文: | 66th Annual IEEE International Electron Devices Meeting, IEDM 2020 | 摘要: | For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration. ? 2020 IEEE. For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration. © 2020 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85102917891&doi=10.1109%2fIEDM13553.2020.9372001&partnerID=40&md5=31013973a9e46607a532c9c76ed8e15c https://scholars.lib.ntu.edu.tw/handle/123456789/581011 |
ISSN: | 01631918 | DOI: | 10.1109/IEDM13553.2020.9372001 | SDG/關鍵字: | Chemical bonds; Electron devices; Silicon wafers; Surface treatment; Temperature; Bonding techniques; Chemical treatments; Heterogeneous integration; Layer transfer; Low temperatures; Multi-channel structure; Two channel; Wafer scale; Wafer bonding |
顯示於: | 電機工程學系 |
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