A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking Time
Journal
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Pages
95-98
Date Issued
2019
Author(s)
Abstract
A sub-sampling phase-locked loop (SSPLL) is presented to tolerate the supply interference and have a short re-locking time. A sampling phase detector, a voltage-to-current converter and a mini-dead zone creator are presented. The low in-band phase noise of the proposed SSPLL is kept and the power penalty is low. This SSPLL is realized in a 0.18μm CMOS process and its active area is 0.097mm2. The power consumption is 13.59mW from a 1.8V supply. At the output frequency of 2.2 GHz, this SSPLL achieves an in-band phase noise of-115.33dBc/Hz at 100kHz offset frequency with a division ratio of 44. Its root-mean-square jitter integrated from 10kHz to 100MHz is 0.77 ps. ? 2019 IEEE.
SDGs
Other Subjects
Locks (fasteners); Phase locked loops; Phase noise; In-band phase noise; Offset frequencies; Output frequency; Power penalty; Robust operation; Root mean square jitter; Sampling phase detector; Voltage-to-current converters; Phase comparators
Type
conference paper