A 1.22 mW 2.4 GHz PLL Using a Single-Ring-Oscillator-Based Integrator with Background Frequency Calibration

A phase-locked loop (PLL) using a single-ring-oscillator-based integrator with background frequency calibration is presented. By introducing the single-ring-oscillator-based integrator, the in-band phase noise and the power efficiency of the PLL are improved. With background frequency calibration, it allows this PLL to tolerate process, supply voltage, and temperature variations. Moreover, the reference spur will be improved by using timing orthogonal scheme. This PLL is fabricated in 40-nm CMOS process which occupies an active area of 0.0011mm2. Its power consumption is 1.22mW from a 1V supply voltage. The measured phase noise is-100dBc/Hz,-108dBc/Hz and-110dBc/Hz at the offset frequencies of 100kHz, 1MHz, and 10MHz, respectively. The integrated root-mean-square jitter is 1.5psrms, and this PLL achieves a figure-of-merit of-235.6dB. ? 2004-2012 IEEE.