|Title:||Evaluation of analog circuit performance for ferroelectric SOI MOSFETs considering interface trap charges and gate length variations||Authors:||Lu Y.-C
VITA PI-HO HU
|Keywords:||Analog circuits; Capacitance; Electric resistance; Ferroelectricity; Mirrors; Nanoelectronics; Signal processing; Timing circuits; Circuit complexity; Circuit performance; Gate length variation; Induced voltages; Interface trap charge; Negative capacitance; Output resistance; Signal processing applications; MOSFET devices||Issue Date:||2019||Source:||2019 Silicon Nanoelectronics Workshop, SNW 2019||Abstract:||
The performance of ferroelectric SOI (FE-SOI) analog circuits considering the impact of interface trap charge (Nit) and gate length (Lg) variations are analysed for the first time. For FE-SOI MOSFETs, the discharging time (ts), on resistance (Ron) of switch circuit, and output current (Iout) of current mirror show superior immunity to Nit and Lg variations compared to the SOI counterparts. FE-SOI MOSFETs show significant improvements in discharging time (-78% and -31%) at Vdd=0.4V and 1V compared to SOI MOSFETs due to the negative capacitance induced voltage amplification and higher drive current. Besides, FE-SOI switch circuit exhibits lower Ron and better Ron flatness which suppresses distortion for audio and signal processing applications. FE-SOI current mirror with larger output resistance shows better current matching (smaller Iout/Iref) than SOI one, and comparable mirroring performance compared to the stacked SOI current mirror. Therefore, FE-SOI current mirror can significantly reduce the circuit complexity and area penalty while maintaining adequate mirroring accuracy. ? 2019 JSAP.
|Appears in Collections:||電機工程學系|
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