Device Designs of III-V Tunnel FETs for Performance Enhancements through Line Tunneling

In this paper, we analyze the device designs of III-V TFET with line tunneling for on current and average subthreshold swing enhancements. Compared to the conventional TFET with point tunneling, TFET with an epitaxial channel layer between gate and source introduces line tunneling. The onset voltage of line tunneling depends on the effective tunneling barrier (Ebeff) and the thickness of epitaxial layer (Tepi). TFET with larger Ebeff shows larger onset voltage of line tunneling which degrades the average subthreshold swing. Compared with thick Tepi, GaAs0.4Sb0.6/In0.65Ga0.35As TFET with thin Tepi exhibits lower drain current at Vg=0.1V while larger Ion at Vg=0.5V. For TFET with Tepi and line tunneling, Tepi should be optimized to obtain high Ion and low average subthreshold swing. GaAs0.4Sb0.6/In0.65Ga0.35As TFET with Tepi=2nm} and 10nm gate-to-source overlap length (Lovs) shows 3.3X higher Ion (406μ A}/μ m}) and lower subthreshold swing (20.67mV/dec) than the conventional TFET. Thinner source-to-channel lateral junction thickness (TS) and larger gate-to-drain underlap length (Lund) decrease the Ioff and improve the subthreshold swing. ? 2018 IEEE.