|Title:||Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET||Authors:||Lin H.-H
VITA PI-HO HU
|Keywords:||Capacitance; Cutoff frequency; Electric fields; Heterojunctions; III-V semiconductors; Semiconducting gallium; Tunnel field effect transistors; Analog performance; Doping concentration; Negative capacitance; Optimized devices; Overlap length; Tunnel FET (TFET); Vertical electric fields; Vertical tunneling; Tunnels||Issue Date:||2019||Journal Volume:||2019-March||Start page/Pages:||241-246||Source:||Proceedings - International Symposium on Quality Electronic Design, ISQED||Abstract:||
In this work, the device design and analog performance of GaAsSb/InGaAs negative-capacitance vertical-tunnel FET (NCVT-FET) are analyzed compared with TFET. The optimized device design of NCVT-FET is proposed to maximize its vertical tunneling over the corner tunneling. Negative capacitance enhances vertical tunneling more significantly than corner tunneling due to the amplified vertical electric field. The impacts of source overlap length, tunnel layer, and N++ doping concentration have been investigated. The optimized NCVT-FET exhibits small Ioff (10pAμ m) and large Ion405μ A}/μ m) at VDD=0.5V with 14mV/decade sub Vt swing over 4 decades of current were obtained. Moreover, the optimized NCVT-FET shows higher transconductance gm, max(+92%), higher gm/IDS, and larger cutoff frequency fT, max(+75%) compared to TFET. ? 2019 IEEE.
|Appears in Collections:||電機工程學系|
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