Highly Stacked GeSi Nanosheets and Nanowires by Lowerature Epitaxy and Wet Etching
Journal
IEEE Transactions on Electron Devices
Journal Volume
68
Journal Issue
12
Pages
6599-6604
Date Issued
2021
Author(s)
Abstract
The eight stacked Ge0.75Si0.25 nanosheets, the seven stacked Ge0.95Si0.05 nanowires, and the six stacked Ge0.95Si0.05 nanowires without parasitic channels are demonstrated. These highly stacked channels are made from 18 epilayers consisting of a Ge buffer, nine heavily P-doped Ge sacrificial layers, and eight GeSi channel layers with the low growth temperature (350 °C and 375 °C) to ensure the entire epilayers metastable without dislocations in the channels. The isotropic wet etching by H2O2 and NH4OH + H2O2 is used for the channel release and the removal of the parasitic channels, respectively. The delicate interplay between epilayer design and wet etching is implemented to fabricate the highly stacked GeSi channels. High inter-channel uniformity of the eight stacked Ge0.75Si0.25 nanosheets is obtained due to the superior etching selectivity. High I ON per stack and per footprint of the seven stacked Ge0.95Si0.05 nanowires and the six stacked Ge0.95Si0.05 nanowires without parasitic channels are achieved due to the high mobility L 4 valleys and nanowire conduction. The reduced subthreshold slope (SS) and improved I ON I OFF are obtained by parasitic channel removal. The record I ON of 120? μ A per stack (4600? μ A μ m per channel footprint) at V OV = V DS = 0.5 V is reached among reported Ge/GeSi 3-D nFETs. ? 1963-2012 IEEE.
Subjects
Chemical vapor deposition (CVD)
GeSi
highly stacked channels
low temperature
nanosheets
nanowires
phosphorus
wet etching
Epilayers
Germanium
Nanosheets
Nanowires
Silicon
Temperature
Wet etching
Channel layers
Channel uniformity
Etching selectivity
Isotropic wet etching
Low growth temperature
Low temperature epitaxies
Sacrificial layer
Subthreshold slope
Si-Ge alloys
Type
journal article