CMOS ISFETs with 3D-Truncated Sensing Structure Resistant to Scaling Attenuation and Trapped Charge-Induced Offset
Journal
IEEE Sensors Journal
Journal Volume
21
Journal Issue
24
Pages
27282-27289
Date Issued
2021
Author(s)
Teng N.-Y
Abstract
With helps of advancing CMOS technology, ISFETs have achieved great success. However, CMOS-based ISFETs are also suffering problems of scaling attenuation and threshold voltage offset. These problems mainly result from the architecture used to adapt standard CMOS process. To deal with these, we developed a novel CMOS ISFET configuration, namely, 3D-T-ISFET, by building a truncated architecture to expose CMOS process-inherent TiN thin film as the sensing interface. Due to the electrical conductivity of TiN, the signal from the environment can bypass the sensing dielectric and couple to the transistor effectively through the electrical double layer capacitance. Based on our experiments, as the footprint of 8.5{2} {mu } text{m} 2, a 3.21-fold {Delta } text{I}_{D} /pH improvement can be achieved by developed 3D-T-ISFET. At the same time, the 3D-T-ISFET has an about 1.65-fold improvement in SNR compared to the traditional 2D-ISFET. Compared to the 2D-ISFET in a state-of-the-art design, therefore, 3D-T-ISFET exhibits a scaling attenuation-free behavior and becomes less vulnerable to the non-idea effects brought by trapped charges. ? 2001-2012 IEEE.
Subjects
CMOS
electrical double layer
extended gate
ISFET
pH sensing
titanium nitride
Capacitance
CMOS integrated circuits
Interfaces (materials)
Threshold voltage
Tin
CMOS technology
Electrical double layers
Extended gate
Scalings
Standard CMOS process
TiN thin films
Trapped charge
Voltage offsets
Titanium nitride
SDGs
Type
journal article