https://scholars.lib.ntu.edu.tw/handle/123456789/607140
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Li W | en_US |
dc.contributor.author | Ma Y | en_US |
dc.contributor.author | Sun Q | en_US |
dc.contributor.author | Zhang L | en_US |
dc.contributor.author | Lin Y | en_US |
dc.contributor.author | Jiang I.H.-R | en_US |
dc.contributor.author | Yu B | en_US |
dc.contributor.author | HUI-RU JIANG | en_US |
dc.creator | Li W;Ma Y;Sun Q;Zhang L;Lin Y;Jiang I.H.-R;Yu B;Pan D.Z. | - |
dc.date.accessioned | 2022-04-25T06:42:25Z | - |
dc.date.available | 2022-04-25T06:42:25Z | - |
dc.date.issued | 2021 | - |
dc.identifier.issn | 02780070 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85097937426&doi=10.1109%2fTCAD.2020.3042175&partnerID=40&md5=7ac396b3fe2761a2f85c5e48dd2ab5fc | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/607140 | - |
dc.description.abstract | Multiple patterning lithography has been widely adopted in advanced technology nodes of VLSI manufacturing. As a key step in the design flow, multiple patterning layout decomposition (MPLD) is critical to design closure. Due to the $\mathcal {N} \mathcal {P} $ -hardness of the general decomposition problem, various efficient algorithms have been proposed with high-quality solutions. However, with increasingly complicated design flow and peripheral processing steps, developing a high-quality layout decomposer becomes more and more difficult, slowing down further advancement in this field. This article presents $\mathsf {OpenMPL}$ (2020), an open-source layout decomposition framework, with well-separated peripheral processing and core solving steps. Besides, previous algorithms or techniques are inspected and several issues are discovered. We then propose corresponding new algorithms to resolve these issues. The experiments demonstrate the effectiveness of our proposed algorithms and the efficiency of $\mathsf {OpenMPL}$. ? 1982-2012 IEEE. | - |
dc.relation.ispartof | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | - |
dc.subject | Design methodology | - |
dc.subject | layout decomposition | - |
dc.subject | VLSI design | - |
dc.subject | Design | - |
dc.subject | Electronics engineering | - |
dc.subject | Advanced technology | - |
dc.subject | Decomposition problems | - |
dc.subject | Design closure | - |
dc.subject | High-quality solutions | - |
dc.subject | Layout decomposition | - |
dc.subject | Multiple patterning | - |
dc.subject | Processing steps | - |
dc.subject | VLSI manufacturing | - |
dc.subject | Integrated circuits | - |
dc.title | OpenMPL: An Open-Source Layout Decomposer | en_US |
dc.type | journal article | en |
dc.identifier.doi | 10.1109/TCAD.2020.3042175 | - |
dc.identifier.scopus | 2-s2.0-85097937426 | - |
dc.relation.pages | 2331-2344 | - |
dc.relation.journalvolume | 40 | - |
dc.relation.journalissue | 11 | - |
item.openairetype | journal article | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.fulltext | no fulltext | - |
item.grantfulltext | none | - |
item.cerifentitytype | Publications | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
顯示於: | 電機工程學系 |
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