|Title:||Transient Current Enhancement in MIS Tunnel Diodes with Lateral Electric Field Induced by Designed High-Low Oxide Layers||Authors:||Huang S.-W
|Keywords:||Lateral nonuniformity;metal-insulator-semiconductor (MIS) tunnel diodes;transient characteristics;Digital storage;Diodes;Electric fields;Electron tunneling;Leakage currents;Metal insulator boundaries;MIS devices;Schottky barrier diodes;Semiconductor insulator boundaries;Transient analysis;Lateral nonuniformity;Metal-insulator-semiconductor tunnel diode;Metal-insulator-semiconductors;Nonuniformity;Oxide layer;Schottky diodes;Steady state;Transient characteristic;Transient characteristic.;Tunneling;Silicon||Issue Date:||2021||Journal Volume:||68||Journal Issue:||12||Start page/Pages:||6580-6585||Source:||IEEE Transactions on Electron Devices||Abstract:||
In this work, the steady-state and transient behavior of the metal-insulator-semiconductor tunnel diodes with designed high-low (H/L) oxide layers were studied, by performing experiments and TCAD simulations. The H/L oxide layers were formed by thickening the oxide around the gate edge while still in a tunneling-transparent thickness. This could reduce the leakage or tunneling current at reverse bias by decreasing the minority carrier density near the gate edge via the induced lateral electric field caused by H/L oxides. The characteristics of devices with various designed parameters were under investigation to discover the necessary conditions for the tunneling current reduction. Due to the leakage current reduction, the enhancement of transient current was found out, accompanied with enlarged transient capacitance change. Steady-state and transient simulation could help to confirm the observed phenomenon and also illustrated the existence of lateral electron current flow that reduced the minority carrier density near the gate edge at reverse bias. A memory operation using the H/L device was demonstrated. The read current at 120 ms improved more than an order of magnitude in current window with respect to planar. The stable performance under endurance testing made the H/L device a possible future volatile memory application. ? 1963-2012 IEEE.
|Appears in Collections:||電機工程學系|
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