https://scholars.lib.ntu.edu.tw/handle/123456789/607186
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin J.-Y | en_US |
dc.contributor.author | JENN-GWO HWU | en_US |
dc.creator | Lin J.-Y;Hwu J.-G. | - |
dc.date.accessioned | 2022-04-25T06:42:37Z | - |
dc.date.available | 2022-04-25T06:42:37Z | - |
dc.date.issued | 2021 | - |
dc.identifier.issn | 00189383 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85110795175&doi=10.1109%2fTED.2021.3095052&partnerID=40&md5=6a61103615013d01e3b1b29727358614 | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/607186 | - |
dc.description.abstract | In this article, a new type of metal-insulator-semiconductor (MIS) tunnel diode (TD), trench MIS TD, was investigated. From the current-voltage characteristics, memory retention, and memory endurance measurements, we found that the trench MIS TDs not only have lower reverse bias current, but also show stronger transient current compared to traditional planar structure MIS TDs. For example, in the 1000-cycle memory endurance test, we observed a 25 times larger current window (CW) in trench devices than the CW of planar devices. We attribute the lower reverse bias current to the fewer minority carriers (electrons) in trench MIS TDs, which is supported by the high-frequency capacitance-voltage (C-V) measurement. As for the enhanced transient behavior of trench MIS TDs, we proposed a mechanism based on the understanding of fewer minority carriers in trench devices to explain our observation. Eventually, we examined the effect of different equivalent oxide thicknesses (EOTs) on the CW and found that the trench devices have better CW in a wide EOT range. Because of the enhanced transient behavior leading to better memory CW, trench MIS TDs have the potential to serve as memory devices. ? 1963-2012 IEEE. | - |
dc.relation.ispartof | IEEE Transactions on Electron Devices | - |
dc.subject | Metal-insulator-semiconductor (MIS) | - |
dc.subject | transient behavior | - |
dc.subject | trench structure | - |
dc.subject | tunnel diode (TD) | - |
dc.subject | Bias voltage | - |
dc.subject | Capacitance | - |
dc.subject | Charge carriers | - |
dc.subject | Current voltage characteristics | - |
dc.subject | Metal insulator boundaries | - |
dc.subject | Tunnel diodes | - |
dc.subject | High frequency capacitance | - |
dc.subject | Mechanism-based | - |
dc.subject | Memory retention | - |
dc.subject | Metal-insulator-semiconductors | - |
dc.subject | Minority carrier | - |
dc.subject | Planar structure | - |
dc.subject | Transient behavior | - |
dc.subject | Transient current | - |
dc.subject | MIS devices | - |
dc.title | Enhanced Transient Behavior in MIS(p) Tunnel Diodes by Trench Forming at the Gate Edge | en_US |
dc.type | journal article | en |
dc.identifier.doi | 10.1109/TED.2021.3095052 | - |
dc.identifier.scopus | 2-s2.0-85110795175 | - |
dc.relation.pages | 4189-4194 | - |
dc.relation.journalvolume | 68 | - |
dc.relation.journalissue | 9 | - |
item.fulltext | no fulltext | - |
item.openairetype | journal article | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.grantfulltext | none | - |
item.cerifentitytype | Publications | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.orcid | 0000-0001-9688-0812 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
顯示於: | 電機工程學系 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。