Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization
Journal
Proceedings -Design, Automation and Test in Europe, DATE
Journal Volume
2021-February
Pages
1026-1031
Date Issued
2021
Author(s)
Abstract
Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area. If the function is completely-specified, the implementation accurately represents the function. If the function is incompletely-specified, the implementation has to be true only on the care set. While most of the algorithms in logic synthesis rely on SAT and Boolean methods to exactly implement the care set, we investigate learning in logic synthesis, attempting to trade exactness for generalization. This work is directly related to machine learning where the care set is the training set and the implementation is expected to generalize on a validation set. We present learning incompletely-specified functions based on the results of a competition conducted at IWLS 2020. The goal of the competition was to implement 100 functions given by a set of care minterms for training, while testing the implementation using a set of validation minterms sampled from the same function. We make this benchmark suite available and offer a detailed comparative analysis of the different approaches to learning. ? 2021 EDAA.
Subjects
Commerce
Fintech
Logic design
Logic Synthesis
Machine learning
Approaches to learning
Benchmark suites
Comparative analysis
Hardware design
Incompletely specified functions
Minterms
Structural representation
Training sets
Computer circuits
SDGs
Type
conference paper