https://scholars.lib.ntu.edu.tw/handle/123456789/607246
標題: | A computational efficient architecture for extremely sparse stereo network | 作者: | Huang T Wu S.-S Klopp J Yu P.-H LIANG-GEE CHEN |
關鍵字: | Deconvolution;Memory mapping;PE utilization;Sparsity-aware CNN;VLSI architecture;Convolution;Memory architecture;Computational requirements;Efficient architecture;Hardware implementations;High utilizations;Processing elements;Proposed architectures;Software implementation;Stereo matching method;Network architecture | 公開日期: | 2021 | 卷: | 2021-May | 來源出版物: | Proceedings - IEEE International Symposium on Circuits and Systems | 會議論文: | 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 | 摘要: | CNN-based stereo matching methods achieve great performance but come with high computational requirements. Pruning a CNN can reduce the complexity but may in turn lead to memory conflicts, lowering throughput. Our proposed architecture and memory mapping technique aim at reducing conflicts to exploit extremely sparse stereo matching networks. To maintain a high utilization of processing elements, we decompose the de-convolution operation into several convolution operations. The proposed architecture provides a 2.1× speed up over SCNN. Compared to the software implementation, only 0.01% performance drop is observed, so that the proposed architecture obtains state-of-the-art accuracy compared to existing sparsity aware hardware implementations. ? 2021 IEEE |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85109024208&doi=10.1109%2fISCAS51556.2021.9401565&partnerID=40&md5=d533cd62a649d3003f5f563ea342de70 https://scholars.lib.ntu.edu.tw/handle/123456789/607246 |
ISSN: | 02714310 | DOI: | 10.1109/ISCAS51556.2021.9401565 |
顯示於: | 電機工程學系 |
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