https://scholars.lib.ntu.edu.tw/handle/123456789/607246
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Huang T | en_US |
dc.contributor.author | Wu S.-S | en_US |
dc.contributor.author | Klopp J | en_US |
dc.contributor.author | Yu P.-H | en_US |
dc.contributor.author | LIANG-GEE CHEN | en_US |
dc.creator | Huang T;Wu S.-S;Klopp J;Yu P.-H;Chen L.-G. | - |
dc.date.accessioned | 2022-04-25T06:42:56Z | - |
dc.date.available | 2022-04-25T06:42:56Z | - |
dc.date.issued | 2021 | - |
dc.identifier.issn | 02714310 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85109024208&doi=10.1109%2fISCAS51556.2021.9401565&partnerID=40&md5=d533cd62a649d3003f5f563ea342de70 | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/607246 | - |
dc.description.abstract | CNN-based stereo matching methods achieve great performance but come with high computational requirements. Pruning a CNN can reduce the complexity but may in turn lead to memory conflicts, lowering throughput. Our proposed architecture and memory mapping technique aim at reducing conflicts to exploit extremely sparse stereo matching networks. To maintain a high utilization of processing elements, we decompose the de-convolution operation into several convolution operations. The proposed architecture provides a 2.1× speed up over SCNN. Compared to the software implementation, only 0.01% performance drop is observed, so that the proposed architecture obtains state-of-the-art accuracy compared to existing sparsity aware hardware implementations. ? 2021 IEEE | - |
dc.relation.ispartof | Proceedings - IEEE International Symposium on Circuits and Systems | - |
dc.subject | Deconvolution | - |
dc.subject | Memory mapping | - |
dc.subject | PE utilization | - |
dc.subject | Sparsity-aware CNN | - |
dc.subject | VLSI architecture | - |
dc.subject | Convolution | - |
dc.subject | Memory architecture | - |
dc.subject | Computational requirements | - |
dc.subject | Efficient architecture | - |
dc.subject | Hardware implementations | - |
dc.subject | High utilizations | - |
dc.subject | Processing elements | - |
dc.subject | Proposed architectures | - |
dc.subject | Software implementation | - |
dc.subject | Stereo matching method | - |
dc.subject | Network architecture | - |
dc.subject.classification | [SDGs]SDG16 | - |
dc.title | A computational efficient architecture for extremely sparse stereo network | en_US |
dc.type | conference paper | en |
dc.relation.conference | 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 | - |
dc.identifier.doi | 10.1109/ISCAS51556.2021.9401565 | - |
dc.identifier.scopus | 2-s2.0-85109024208 | - |
dc.relation.journalvolume | 2021-May | - |
item.cerifentitytype | Publications | - |
item.fulltext | no fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.openairetype | conference paper | - |
item.grantfulltext | none | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Networking and Multimedia | - |
crisitem.author.orcid | 0000-0001-9746-9355 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
顯示於: | 電機工程學系 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。