Design of Sub-Sampling Phase-Locked Loop with a Time-Based Loop Filter
Journal
2021 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2021
Date Issued
2021
Author(s)
Abstract
This paper implements a phase-locked loop based on ring-oscillator operating at 2.4GHz in a TSMC 180 nm CMOS process. It combines a sub-sampling and time-based integrator technology. First, the sub-sampling feature is used to reduce in-band phase noise. However, because of the subsampling characteristic, the demand for capacitor on the loop filter is even greater. In order to avoid the loss and cost of extra area, the traditional capacitor can be replaced by the current-controlled ring-oscillator for storing phase through based on time integrator technology, so a lot of area can be saved. This chip is operated 1.8V power supply, the power consumption is 10.1mW, its core circuit area is about 0.024mm2, when the input reference frequency is 150MHz, the out-put frequency is 2.4GHz. The phase noise performance is-104.1dBc/Hz at 1-MHz frequency offset, and the reference spur is-37.84dBc. ? 2021 IEEE.
Event(s)
2021 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2021
Subjects
current-controlled ring-oscillator (CCRO)
phase-locked loop (PLL)
small area
sub-sampling
Frequency allocation
Locks (fasteners)
Phase noise
Current controlled ring oscillators
Current-controled ring-oscillator
Loop filter
Phase-locked loop
Ring oscillator
Sampling phasis
Sampling-based
Small area
Sub-sampling
Time based
Phase locked loops
SDGs
Type
conference paper