https://scholars.lib.ntu.edu.tw/handle/123456789/607291
標題: | A Wide-Range FD for Referenceless Baud-Rate CDR Circuits | 作者: | Yao Y.-S Huang C.-C SHEN-IUAN LIU |
關鍵字: | Baud rate;clock and data recovery;decision feedback equalizer;frequency detector;quarter-rate;Decision feedback equalizers;Energy efficiency;Finite difference method;Timing circuits;Active area;Clock and data recovery;CMOS technology;Data rates;Frequency captures;Frequency detectors;Lock time;Quarter-rate;Clock and data recovery circuits (CDR circuits) | 公開日期: | 2022 | 卷: | 69 | 期: | 1 | 起(迄)頁: | 60-64 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A wide-range frequency detector (FD) is presented for baud-rate clock and data recovery (CDR) circuits. It achieves a wide frequency capture range, a short lock time, and a low power. By using this FD, a referenceless quarter-rate CDR circuit with a one-tap decision feedback equalizer is fabricated in 40-nm CMOS technology. The active area of this CDR circuit is 0.0999mm2 and its power is 44mW while the data rate is 16.8Gbps. The calculated energy efficiency of this CDR circuit is 2.62pJ/b. ? 2004-2012 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85111049256&doi=10.1109%2fTCSII.2021.3087364&partnerID=40&md5=77fd98832518671c442f08b2720ca5ac https://scholars.lib.ntu.edu.tw/handle/123456789/607291 |
ISSN: | 15497747 | DOI: | 10.1109/TCSII.2021.3087364 |
顯示於: | 電機工程學系 |
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