A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC with a Varactor-Based Residue Amplifier
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Date Issued
2022
Author(s)
Abstract
A pipelined SAR ADC is proposed to achieve faster conversion by employing residue conversion and partial bit conversion in parallel to lessen timing constraints. Additionally, a varactor-based dynamic amplifier is adopted to improve linearity for a 10-b accuracy. The single-channel ADC achieves 1 GS/s with a peak SNDR 41.37 dB at a Nyquist input and consumes 9.4 mW. IEEE
Subjects
Analog-digital conversion
Capacitance
Dynamic Amplifier
Linearity
Parallel Conversion
Pipelined SAR ADC
Registers
Single Channel
Switches
Varactor-Based Compensation.
Varactors
Voltage
Analog to digital conversion
Dynamic amplifier
Parallel conversion
Register
Residue conversion
SAR ADC
Single channels
Varactor-based compensation.
SDGs
Type
journal article