Sensitivity Analysis and Design of Negative-Capacitance Junctionless Transistor for High-Performance Applications

In this work, we perform the sensitivity analysis of negative-capacitance (NC) junctionless (JL) transistors considering the variation in device parameters and compared its performance with conventional JL devices. The OFF-current (IOFF) of the JL transistor degrades significantly as the film thickness (Tsi), channel doping (Nch), and oxide thickness (Tox) increase and the gate length (Lg) decreases. However, compared to JL devices, IOFF degradation due to increasing Tsi and Nch and decreasing Lg can be effectively mitigated in NCJL devices. The reduced IOFF and lower IOFF sensitivities in the NCJL transistor are due to the occurrence of more negative internal gate voltage at higher Tsi and Nch and lower Lg, which enhances the channel depletion and reduces the IOFF sensitivity. The impact of Tox and the spacer permittivity (s) shows that reducing Tox and increasing s significantly improve the ON-current in NCJL devices due to better capacitance matching at the ON-state. Besides, for the first time, a design methodology is proposed to optimize the NCJL device for high-performance (HP) applications at Lg = 15 nm. The results presented in this article serve as a guideline to extend the usability of NCJL devices for HP applications. ? 1963-2012 IEEE.